1. Field of the Invention
The present invention relates generally to a bus driving circuit for driving a bus line provided in a large scale integrated circuit. More specifically, the invention relates to a bus driving circuit used for transferring output data from a pre-charge type circuit via a bus line.
2. Description of the Prior Art
In recent years, large scale integrated circuits (LSIs) are large-scaled and accelerated at a request for the advance of the fine patterning technology and the improvement of the system performance.
As microprocessors, LSIs having a plurality of circuit blocks therein have a bus line for connecting these circuit blocks.
For example, as shown in FIG. 3, a large memory unit 30 built in a microprocessor is separated into a plurality of memory blocks 301, 302, 303 and 304 by addresses. The data output terminals of these memory blocks are connected to a bus line 10 via a read circuit 32 and a bus driving circuit 40. Such a bus line 10 is driven by the bus driving circuit 40 of an activated one of the memory blocks to transfer data to the next stage circuit.
FIG. 4 shows a conventional bus driving circuit. This bus driving circuit 40A comprises: a tristate buffer 44 comprising a P-channel MOSFET 44a and an N-channel MOSFET 44b; and a gate control circuit 42 for controlling the gate of each of the MOSFETs of the tristate buffer 44 on the basis of an enable signal and input data.
The gate control circuit 42 comprises an AND gate 42a, an inverter 42b and an OR gate 42c. The AND gate 42a performs an AND operation on the basis of the enable signal and the input data to transmit the operated results to the gate of the N-channel MOSFET 44b. The OR gate 42c performs an OR operation on the basis of the input data and a signal produced by inverting the enable signal by the inverter 42b, to transmit the operated results to the gate of the P-channel MOSFET 44a. Furthermore, the input data are produced in synchronism with a clock signal. The output of the tristate buffer 44 is connected to the bus line 10.
The operation of the bus driving circuit 40A is as follows. When the enable signal is inactive, the output of the tristate buffer 44 has high impedance so as not to drive the bus line 10. At this time, if the bus driving circuit 40A is connected to one memory block of the memory unit 30 shown in FIG. 3, other memory blocks are activated, and other bus driving circuits connected to the activated memory blocks drive the bus line 10 to perform data transfer.
On the other hand, if the enable signal inputted to the bus driving circuit 40A is activated, the bus line 10 is driven in accordance with the input data to perform data transfer as shown in FIG. 5. Furthermore, as shown in FIG. 4, an inverter 50 and a latch circuit 60 controlled by a clock signal CK are provided on the next stage circuit side, to which data are transferred. The potential of the bus line 10 holds data until the next memory access is started (until the clock signal CK is raised next time) (see FIG. 5)
FIG. 6 shows another example of a conventional bus driving circuit. In a bus driving circuit 40B shown in FIG. 6, the gate control circuit 42 of the bus driving circuit 40A shown in FIG. 4 is replaced with a gate control circuit 43. The gate control circuit 43 comprises an AND gate 43a. The AND gate 43a performs an AND operation on the basis of input data and an enable signal to transmit the operated results to the gate of an N-channel MOSFET 44b of a tristate buffer 44. Furthermore, to the gate of a P-channel MOSFET 44a of the tristate buffer 44, an inverted signal /PC of a pre-charge signal PC synchronized with a clock signal is inputted.
The conventional bus driving circuit 40B shown in FIG. 6 is designed to receive, as data input, the output of a pre-charge type circuit, i.e., a circuit wherein its output is previously set at a low potential and wherein the data transition of the output occurs only when a high potential is outputted. Furthermore, a read circuit 32 for reading data from the memory unit 30 shown in FIG. 3 is a pre-charge type circuit.
Referring to FIG. 7, the operation of the bus driving circuit 40B, which is shown in FIG. 6 and which is applied to the memory unit 30, will be described below.
The bus driving circuit 40B turns the P-channel MOSFET 44a ON, in response to the pre-charge signal PC during a memory access, to previously set the bus line 10 at the high potential. Thereafter, although the MOSFET 44a is turned OFF, the bus line is held to be the high potential by a latch circuit 70. Furthermore, the latch circuit 70 is provided on the side of a circuit, to which data are transferred. In such a state, if the enable signal is activated and if high potential data are outputted from the read circuit 32 of the memory unit 30, the N-channel MOSFET 44b is turned ON, so that the bus line 10 is driven at a low potential to perform data transfer (see FIG. 7). The potential of the bus line 10 is held by the latch circuit 70 even after the memory access ends to set the output of the read circuit 32 at a low potential again until the next memory access is started to pre-charge the bus line 10 by the pre-charge signal /PC (see FIG. 7)
As described above, the potential of the bus line 10 connected to the conventional bus driving circuit 40B shown in FIG. 6 is held by the latch circuit 70 until the bus line 10 is pre-charged by the pre-charge signal /PC even after the memory access ends to set the output of the read circuit 32 at the low potential again. Therefore, since it is not required to provide the latch circuit 60 for operating in response to the clock signal, which is provided at the next stage of the bus line 10 as shown in FIG. 4, the number of gate stages can be smaller than that of the bus driving circuit 40A shown in FIG. 4, and the data transfer can be rapidly carried out.
However, the bus driving circuit shown in FIG. 6 is weak in noises since the bus line 10 remains being held at the high potential by the latch circuit 70 having a weak driving force when the output of the read circuit 32 has a low potential. In particular, the bus lines 10 are arranged in parallel at a long distance, and the data transitions occur simultaneously, so that there is much noise due to the coupling capacity with the next line.
Therefore, if the next bus line is driven at the low potential, there is some possibility that the potential of the bus line to be held at the high potential changes to the low potential under the influence of the coupling capacity to cause malfunction.
According to one aspect of the present invention, a memory unit includes a plurality of memory cells arranged in the form of a matrix: word lines for selecting memory cells on the same line; bit lines for transmitting the potential levels of the memory cells selected by the word lines; a bit line pre-charge circuit for pre-charging the bit lines; a sense amplifier circuit for amplifying the potentials of the memory cells which are read to the bit lines; bus pre-charge means for pre-charging a bus line on the basis of a pre-charge signal produced in synchronism with a clock signal; a tristate buffer for driving the bus line on the basis of a gate control signal; and a gate control circuit for transmitting the gate control signal to the tristate buffer so as not to drive the bus line when an enable signal is in an inactive state, and for transmitting the gate control signal to the tristate buffer so as to drive the bus line on the basis of the potential of the bus line the output data of the sense amplifier circuit when the enable signal is in an active state.
The gate control circuit may output first and second gate control signals, and the tristate buffer may include a first MOSFET of a first conductive type, which has a source connected to a first power supply, a gate for receiving the first gate control signal, and a drain connected to the bus line; and a second MOSFET of a second conductive type different from the first conductive type, the second MOSFET having a source connected to a second power supply for supplying a lower potential than that of the first power supply, a gate for receiving the second gate control signal, and a drain connected to the drain of the first MOSFET, the first MOSFET being turned ON only when the potential of the bus line is a logical value xe2x80x9cHxe2x80x9d.
The bus pre-charge means may hold the input data on the bus line by pre-charging the bus line only during an access operation for the pre-charge circuit.
The first MOSFET may be a P-channel MOSFET, and the second MOSFET may be an N-channel MOSFET.
The gate control circuit may include an AND gate for performing an AND operation on the basis of the enable signal and the input data to output the second gate control signal; a NAND gate for performing a NAND operation on the basis of the enable signal and the potential of the bus line; and an OR gate for performing an OR operation on the basis of the input data and the output of the NAND gate to output the first gate control signal.
The bus pre-charge means may be a P-channel MOSFET.